
COMMERCIALTEMPERATURERANGE
4
IDTCV133
PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR
PIN DESCRIPTION (CONT.)
Pin Number
Name
Type
Description
43
CPU0#
OUT
Host 0.7 current mode differential clock output
44
CPU0
OUT
Host 0.7 current mode differential clock output
45
VSS_CPU
GND
46
SCL
I N
SM bus clock
47
SDA
I/O
SM bus data
48
VDD_REF
PWR
3.3V
49
XTAL_OUT
OUT
XTALoutput
50
XTAL_IN
I N
XTALinput
51
VSS_REF
GND
52
REF
OUT
14.318 MHz reference clock output
53
FSC/TEST_SEL
I N
CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted LOW.
54
CPU_STOP#
I N
Stop all stoppable CPU CLK
55
PCI_STOP#
I N
Stop all stoppable PCI, SRC CLK
56
PCI0
OUT
PCI clock
INDEX BLOCK WRITE PROTOCOL
Bit
# of bits
From
Description
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Ack (Acknowledge)
11-18
8
Master
Register offset byte (starting byte)
19
1
Slave
Ack (Acknowledge)
20-27
8
Master
Byte count, N (0 is not valid)
28
1
Slave
Ack (Acknowledge)
29-36
8
Master
first data byte (Offset data byte)
37
1
Slave
Ack (Acknowledge)
38-45
8
Master
2nd data byte
46
1
Slave
Ack (Acknowledge)
:
Master
Nth data byte
Slave
Acknowledge
Master
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit
# of bits
From
Description
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Ack (Acknowledge)
11-18
8
Master
Register offset byte (starting byte)
19
1
Slave
Ack (Acknowledge)
20
1
Master
RepeatedStart
21-28
8
Master
D3h
29
1
Slave
Ack (Acknowledge)
30-37
8
Slave
Byte count, N (block read back of N
bytes), power on is 8
38
1
Master
Ack (Acknowledge)
39-46
8
Slave
first data byte (Offset data byte)
47
1
Master
Ack (Acknowledge)
48-55
8
Slave
2nd data byte
Ack (Acknowledge)
:
Master
Ack (Acknowledge)
Slave
Nth data byte
Not acknowledge
Master
Stop
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.